Liquid ejecting apparatus, drive circuit, and head unit

ABSTRACT

A liquid ejecting apparatus includes an ejecting unit that includes a piezoelectric element which is displaced by a drive signal; a differential amplifier that outputs a control signal based can a source drive signal which is a source signal of the drive signal and a signal based on the drive signal; a pair of transistors that include a high-side transistor and a low-side transistor which are controlled based on the control signal and outputs the drive signal from an output terminal; and a selector that selects one of the high-side transistor and the low-side transistor and supplies the control signal to the selected transistor. The selector selects a transistor to which the control signal is supplied, based on a logic level of a predetermined select signal. The logic level of the select signal is inverted for a predetermined period.

The entire disclosure of Japanese Patent Application No. 2014-034994,filed Feb. 26, 2016 is expressly incorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to a liquid ejecting apparatus, a drivecircuit, and a head unit.

2. Related Art

An ink jet printer which uses a piezoelectric element (for example, apiezo element) and which prints an image or a text by ejecting ink isknown. Piezoelectric elements are provided in correspondence withmultiple nozzles in a bead unit, each of the piezoelectric elements isdriven in accordance with a drive signal, and thereby, a predeterminedamount of ink (liquid) is ejected from the nozzle at a predeterminedtiming to form dots. The piezoelectric element is electrically acapacitive element like a capacitor, and needs to receive a sufficientcurrent in order to operate the piezoelectric element of each nozzle.

Accordingly, a source drive signal which is a source signal of a drivesignal is amplified by an amplification circuit, is supplied to s headunit as a drive signal, and drives the piezoelectric elements. Anamplification circuit uses a method (linear amplification, refer toJP-A-2009-190287) of amplifying current for the source drive signal in aclass AB amplification or the like. However, since power consumptionincreases and energy efficiency decreases in the linear amplification, aclass D amplification is also proposed in recent years (refer toJP-A-2010-114711). In short, in a class D amplification, a pulse widthmodulation or a pulse density modulation of the source drive signal isperformed, a high-side translator and a low-side translator that oreinserted in series between power supply voltages are switched inaccordance with the modulated signal, an output signal which isgenerated by the switching is filtered by a low pass filter, and thus,the source drive signal is amplified.

Energy efficiency of a class D amplification method is higher than thatof a linear amplification method, however, power which is consumed by alow pass filter cannot be ignored, and thus, there is room forimprovement in terms of reducing power consumption.

SUMMARY

An advantage of some aspects of the invention provide liquid ejectingapparatus, a drive circuit, and a head unit which reduce powerconsumption.

A liquid ejecting apparatus according to an aspect of the inventionincludes an ejecting unit that includes a piezoelectric element which isdisplaced by a drive signet being applied to the piezoelectric elementand ejects liquid in accordance with displacement of the piezoelectricelement; a differential amplifier that outputs a control signal based ona source drive signal which is a source signal of the drive signal and asignal based on the drive signal a pair of transistors that include ahigh-side transistor and a low-side transistor which are controlledbased on the control signal and outputs the drive signal from an outputterminal; a selector that selects one of the high-side translator endthe low-side translator and supplies the control signal to the selectedtranslator; a first resistance element for pulling up the outputterminal; and a second resistance element for pulling down the outputterminal. The selector selects a transistor to which the control signalis supplied, based on a logic level of a predetermined select signal.The select signal designates selection in the select unit, based on avoltage of the source drive signal. The logic level of the select signalis inverted for a predetermined period when a difference between avoltage of the source drive signal end a voltage of signal based on thedrive signal is larger than or equal to a threshold value.

According to the liquid ejecting apparatus of the aspect, a low passfilter is not needed compared with a class D amplification method, andthus, power which is consumed by the low pass filter can be ignored andpower consumption is reduced by the amount consumed. Furthermore, alogic level of a select signal is inverted during a predeterminedperiod, and thereby, a waveform of a drive signal is corrected, andthus, it is possible to improve waveform reproducibility. For example,inversion of a logic level of a select signal during a predeterminedperiod is typically performed by inserting a pulse. In addition, anoperational amplifier, a comparator, or the like can be used for adifferential amplifier.

In the liquid ejecting apparatus according to the aspect, a resistancevalue of the first resistance element or a resistance value of thesecond resistance element may vary, and the resistance value may changewhen a difference between the voltage of the source drive signal and thevoltage of the signal based on the drive signal is larger than or equalto the threshold value.

In addition, in the liquid ejecting apparatus according to the aspect,the selector may select the high-side transistor in a period in which avoltage of the drive signal increases, and selects the low-sidetransistor in a period in which the voltage of the drive signaldecreases.

In the liquid ejecting apparatus according to the aspect, the selectormay select the high-side translator in a period in which the drivesignal is constant at a voltage higher than or equal to a predeterminedthreshold voltage, and may select the low-side transistor in a period inwhich the drive signal is constant at a voltage lower than thepredetermined threshold voltage.

In the configuration, the threshold voltage may be lower than a maximumvalue of a voltage of the drive signal, and can be higher than a minimumvalue of the voltage of the drive signal.

The liquid ejecting apparatus may be a device which ejects liquid, andincludes a three-dimensional shaping apparatus (so-called 3D printer), atextile printing apparatus, or the like, in addition to a printingapparatus which will be described below.

In addition, the invention is not limited to a liquid ejectingapparatus, can be realized in various aspects, and can be conceptualizedas a drive circuit which drives a capacitive lead such as thepiezoelectric element, a head unit of a liquid ejecting apparatus, orthe like.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings, wherein like numbers reference like elements.

FIG. 1 is a perspective view illustrating a schematic configuration of aprinting apparatus (Example 1) according to an embodiment.

FIG. 2A is a diagram illustrating arrangement or the like of nozzles ina head unit.

FIG. 2B is a diagram illustrating arrangement or the like of the nozzlesin the head unit.

FIG. 3 is a sectional view illustrating a main configuration of the headunit.

FIG. 4 is a block diagram illustrating an electrical configuration ofthe printing apparatus (Example 1).

FIG. 5 is a diagram illustrating waveforms and the like of drivesignals.

FIG. 6 is a diagram illustrating a configuration of a select controlunit.

FIG. 7 is a diagram illustrating decoded content of a decoder.

FIG. 8 is a diagram illustrating a configuration of a select unit.

FIG. 9 is a diagram illustrating the drive signals which are suppliedfrom the select unit to a piezoelectric element.

FIG. 10 is e diagram illustrating a drive circuit (Example 1) which isapplied to the printing apparatus (Example 1).

FIG. 11 is a diagram illustrating an operation of the drive circuit(Example 1).

FIG. 12 is a diagram illustrating a drive circuit (Example 2).

FIG. 13 is a block diagram illustrating an electrical configuration of aprinting apparatus (Example 2).

FIG. 14 is a diagram illustrating a drive circuit (Example 3) which isapplied to the printing apparatus (Example 2).

FIG. 15 is a diagram illustrating an operation of a drive circuit(Example 3).

FIG. 16 is a diagram illustrating a drive circuit (Example 4).

FIG. 17 is a block diagram illustrating a drive circuit (comparativeexample).

FIG. 18 is a diagram illustrating an operation of the drive circuit(comparative example).

FIG. 19 is a diagram illustrating an operation of the drive circuit(comparative example).

DESCRIPTION OP EXEMPLARY EMBODIMENTS

Hereinafter, a printing apparatus according to an exemplary embodimentof the invention will be described with reference to the drawings.

FIG. 1 is a perspective view illustrating a schematic configuration of aprinting apparatus (Example 1).

The printing apparatus (Example 1) illustrated in this figure is a typeof liquid ejecting apparatus which ejects ink that is an example ofliquid, thereby, forming an ink dot group on a medium P such as paper,thereby, printing an image (including characters, graphics, or thelike).

In the printing apparatus, a symbol is unified by 1 for the sake ofconvenience, but since there are several aspects as will be describebelow, there is a case where parenthesis such as printing apparatus(Example 1) or a printing apparatus (Example 2) is attached instead of asymbol so that each of them is distinguished.

As illustrated in FIG. 1, the printing apparatus 1 includes a movingmechanism 6 which moves (moves back and forth) a carriage 20 in a mainscanning direction (X direction).

The moving mechanism 4 includes a carriage motor 61 which moves thecarriage 20, a carriage guide axle 62 both of which are fixed, and atiming belt 63 which extends substantially parallel to the carriageguide axis 62 and is driven by the carriage motor 61.

The carriage 20 is supported by the carriage guide axis 62 so as to movefreely back and forth, and is fixed to a part of the timing belt 63.Accordingly, if the timing belt 63 travels forward and backward by thecarriage motor 61, the carriage 20 is guided by the carriage guide axis62 and move back and forth.

A printing bead 22 is mounted in the carriage 20. The printing head 22includes multiple nozzles which respectively eject ink in the Zdirection onto a portion which faces the medium P. The printing head 22is divided into approximately four blocks for color printing. Themultiple blocks respectively eject black (Bk) ink, cyan (C) ink, magenta(M) ink, and yellow (Y).

There is provided a configuration in which various control signals orthe like, which include a drive signal from a main substrate (omitted inFIG. 1) through a flexible flat cable 190, are supplied to the carriage20.

The printing apparatus 1 includes a transport mechanism 8 whichtransports the medium P on a platen 80. The transport mechanism 8includes a transport motor 81 which is a drive source, and a transportroller 82 which is rotated by the transport motor 81 and transports themedium P in a sub-scanning direction (Y direction).

In the configuration, an image is formed on a surface of the medium P byejecting ink in response to print data from the nozzles of the printinghead 22 in accordance with main scanning of the carriage 20, andrepeating an operation of transporting the medium P in accordance withthe transport mechanism 8.

In the present embodiment, the main scanning is performed by moving thecarriage 20, but may be performed by moving the medium P, and may beperformed by moving both the carriage 20 and the medium P. The point isthat there may be provided a configuration in which the medium P and thecarriage 20 (printing head 22) move relatively.

FIG. 2A is a diagram illustrating a configuration in a case in which anejecting surface of ink in the printing head 22 is viewed from themedium P. As illustrated in FIG. 2A, the printing head 22 includes fourbead units 3. The four head units 3 are arranged in the X directionwhich is a main scanning direction in correspondence with black (Bk),cyan (C), magenta (M), and yellow (Y), respectively.

FIG. 2B is a diagram illustrating arrangement of nozzles in one headunit 3.

As illustrated in FIG. 2B, multiple nozzles N are arranged in twocolumns in one head unit 3. For the sake of convenience, the two columnsare respectively referred to as a nozzle column Na and a nozzle columnNb.

Multiple nozzles N are respectively arranged in the Y direction which isa subscan direction by a pitch P1 in the nozzle columns Na and Nb. Inaddition, the nozzle columns Na and Nb are separated from each other bya pitch P2 in the X direction. The nozzles N in the nozzle column Na areshifted from the nozzles N in the nozzle column Nb by half of the pitchP1 in the Y direction.

In this way, the nozzles N are arranged so as to be shifted by half ofthe pitch P1 in the two columns of the nozzle columns Na and Nb in the Ydirection, and thereby it is possible to increase resolution in the Ydirection substantially twice as much as a case of one column.

The number of nozzles N in one head unit 3 is referred to as m (m is aninteger greater than or equal to 2) for the sake of convenience.

while not particularly illustrated, the head unit 3 has a configurationin which a flexible circuit board is coupled to an actuator substrate,and a drive IC is mounted on the flexible circuit board. Hence, next, astructure of the actuator substrate will be described.

FIG. 3 is a sectional view illustrating a structure of the actuatorsubstrate. In detail, FIG. 3 is a view illustrating a cross sectiontaken along line III-III of FIG. 2B.

As illustrated in FIG. 3, the actuator substrate 40 has a structure inwhich a pressure chamber substrate 44 and a vibration plate 46 areprovided on a surface on a negative side in the Z direction and a nozzleplate 41 is provided on a surface on a positive side in the Z direction,in a flow path substrate 42.

Schematically, each element of the actuator substrate 40 is a member ofan approximately flat plate which is long in the Y direction, and isfixed to each other by for example, an adhesive or the like. Inaddition, the flow path substrate 42 and the pressure chamber substrate44 are formed by, for example, a single crystal substrate of silicon.

The nozzles N are formed in the nozzle plate 41. A structurecorresponding to the nozzles in the nozzle column Na is shifted from astructure corresponding to the nozzles in the nozzle column Nb by halfof the pitch P1 in the Y direction, but the nozzles are formedapproximately symmetrically except for that, and thus, the structure ofthe actuator substrate 40 will be hereinafter described by focusing onthe nozzle column Na.

The flow path substrate 42 is a flat member which forms a flow path ofink, and includes an opening 422, a supply flow path 424, and acommunication flow path 426. The supply flow path 424 and thecommunication flow path 426 are formed in each nozzle, and the opening422 is continuously formed over the multiple nozzles and has a structurein which ink with a corresponding color is supplied. The opening 422functions as a liquid reservoir chamber Sr, and a bottom surface of theliquid reservoir chamber Sr is configured by, for example, the nozzleplate 41. In detail, the nozzle plate 41 is fixed to the bottom surfaceof the flow path substrate 42 so as to close the opening 422, the supplyflow path 424, and the communication flow path 426 which are in the flowpath substrate 42.

The vibration plate 46 is installed on a surface on a side opposite tothe flow path substrate 42, in the pressure chamber substrate 44. Thevibration plate 46 is a member of an elastically vibratile flat plate,and is configured by stacking an elastic film formed of an elasticmaterial such as a silicon oxide, and an insulating film formed of aninsulating material such as a zirconium oxide. The vibration plate 46and the flow path substrate 42 face each other with an interval in theinner side of each opening 422 of the pressure chamber substrate 44. Aspace between the flow path substrate 42 and the vibration plate 46 inthe inner side of each opening 422 functions as a cavity 442 whichprovides pressure to ink. Each cavity 442 communicates with the nozzle Nthrough the communication flow path 426 of the flow path substrate 42.

A piezoelectric element Pzt is formed in each nozzle N (cavity 442) on asurface on a side opposite to the pressure chamber substrate 44 in thevibration plate 46.

The piezoelectric element Pzt includes a common drive electrode 72formed over the multiple piezoelectric elements Pzt formed on a surfaceof the vibration plate 46, a piezoelectric body 74 formed on a surfaceof the drive electrode 72, and individual drive electrodes 76 formed ineach piezoelectric element Pzt on a surface of the piezoelectric body74. In the configuration, a region in which the piezoelectric body 74 isinterposed between the drive electrode 72 and the drive electrode 76which face each other, functions as the piezoelectric element Pzt.

The piezoelectric body 74 is formed in a process which includes, forexample, a heating process (baking). In detail, the piezoelectric body74 is formed by baking a piezoelectric material which is applied to asurface of the vibration plate 46 on which multiple drive electrodes 72are formed, using heating processing of a furnace, and then molding(milling by using, for example, plasma) the baked material for eachpiezoelectric element Pzt.

In the same manner, the piezoelectric element Pzt corresponding to thenozzle column Nb is also configured to include the drive electrode 72,the piezoelectric body 74, and the drive electrode 76.

In addition, in this example, in the piezoelectric body 74, the commondrive electrode 72 is used as a lower layer and the individual driveelectrodes 76 are used as an upper layer, but in contrast to this, aconfiguration in which the common drive electrode 72 is used as an upperlayer and the individual drive electrodes 76 are used as a lower layer,may be provided.

A configuration may be provided in which the drive IC is directlymounted in the actuator substrate 40.

As will be described below, meanwhile a voltage Vout of a drive signalaccording to the amount of ink to be ejected is individually applied tothe drive electrode 76 which is a terminal of the piezoelectric elementPzt, a retention signal of a voltage V_(BS) is commonly applied to thedrive electrode 72 which is the other terminal of the piezoelectricelement Pzt.

Accordingly, the piezoelectric element Pzt becomes displaced upwardly ordownwardly in accordance with a voltage which is applied to the driveelectrodes 72 and 76. In detail, if the voltage Vout of the drive signalwhich is applied through the drive electrode 76 decreases, the centralportion of the piezoelectric element Pzt is bent upwardly with respectto both end portions, and meanwhile, if the voltage Vout increases, thecentral portion of the piezoelectric element Pzt is bent downwardly.

If the central portion is bent upwardly, an internal volume of thecavity 442 increases (pressure decreases), and thus ink is drawn fromthe liquid reservoir chamber Sr. Meanwhile, if the central portion isbent downwardly, an internal volume of the cavity 442 decreases(pressure increases), and thus, an ink droplet is ejected from thenozzle N in accordance with the decreased degree. In this way, if aproper drive signal is applied to the piezoelectric element Pzt, ink isejected from the nozzle N in accordance with the displacement of thepiezoelectric element Pzt. Accordingly, an ejecting unit which ejectsink in accordance with at least the piezoelectric element Pzt, thecavity 442, or the nozzle N, is configured.

Next, an electrical configuration of the printing apparatus 1 will bedescribed.

FIG. 4 is a block diagram illustrating an electrical configuration ofthe printing apparatus 1.

As illustrated in FIG. 4, the printing apparatus 1 has a configurationin which the head unit 3 is coupled to a main substrate 100. The headunit 3 is largely divided into the actuator substrate 40 and a drive IC50.

The main substrate 100 supplies a control signal Ctr or drive signalsCOM-A and COM-B to the drive IC 50, and supplies a retention signal ofthe voltage V_(BS) (offset voltage) to the actuator substrate 40 througha wire 550.

In the printing apparatus 1, four head units 3 are provided, and themain substrate 100 independently controls the four head units 3. Thefour head units 3 are the same as each other except that the colors ofink to be ejected are different from each other, and thus, hereinafter,one head unit 3 will be representatively described for the sake ofconvenience.

As illustrated in FIG. 4, the main substrate 100 includes a control unit110, D/A converters (DAC) 113 a and 113 b, voltage amplifiers 115 a and115 b, drive circuits 120 a and 120 b, and an offset voltage generationcircuit 130.

Among these, the control unit 110 is a type of a microcontroller havinga CPU, a RAM, a ROM, and the like, and outputs various control signalsor the like for controlling each unit by executing a predeterminedprogram, when image data which becomes a printing target is suppliedfrom a host computer or the like.

In detail, first, the control unit 110 repeatedly supplies digital datadA to the DAC 113 a and the drive circuit 120 a, and repeatedly suppliesdigital data dB to the DAC 113 b and the drive circuit 120 b, in thesame manner. Here, the data dA defines a waveform of the drive signalCOM-A which is supplied to the head unit 3, and the data dB defines awaveform of the drive signal COM-B.

The DAC 113 a converts the digital data dA into analog signal ain. Thevoltage amplifier 115 a amplifies a voltage of the signal ain by, forexample, 10 times and supplies the voltage to the drive circuit 120 a asa signal Ain. In the same manner, the DAC 113 b converts the digitaldata dB into analog signal bin, and the voltage amplifier 115 bamplifies a voltage of the signal bin by, for example, 10 times andsupplies the voltage to the drive circuit 120 b as a signal Bin.

The drive circuit 120 a, which will be described below in detail,outputs the signal Ain to the piezoelectric element Pzt which is acapacitive load as the drive signal COM-A by increasing drive capability(converting to low impedance). In the same manner, the drive circuit 120b outputs the signal Bin as the drive signal COM-B by increasing drivecapability.

The drive signal COM-A and COM-B (signals ain and bin after beinganalog-converted, signals Ain and Bin before being impedance-converted)have trapezoidal waveforms as will be described below.

The signal Ain (Bin) which is converted by the DAC 113 a (113 b)performs a relatively small swing in a range of a voltage of, forexample, approximately 0 V to 4 V, and in contrast to this, the drivesignal COM-A (COM-B) performs a relatively large swing in a range of avoltage of, for example, approximately 0 V to 40 V. Accordingly, thereis provided a configuration in which the voltage amplifier 115 a (115 b)amplifies a voltage of the signal ain (bin) which is converted by theDAC 113 a (113 b), and the drive circuit 120 a (120 b)impedance-converts the signal Ain (Bin) whose voltage is amplified.

Second, the control unit 110 supplies various control signals Ctr to thehead unit 3, in synchronization with control for the moving mechanism 6and the transport mechanism 8. The control signals Ctr which aresupplied to the head unit 3 include print data (ejecting control signal)which defines the amount of ink which is ejected from the nozzle N, aclock signal which is used for transmission of the print data, a timingsignal which defines a print period or the like, or the like.

The control unit 110 controls the moving mechanism 6 and the transportmechanism 8, but such a configuration is known, and thus, descriptionthereof will be omitted.

The offset voltage generation circuit 130 in the main substrate 100generates a retention signal of the voltage V_(BS) and commonly appliesthe signal to the other terminals of the multiple piezoelectric elementsPzt in the actuator substrate 40 through the wires 550. The retentionsignal of the voltage V_(BS) maintains the other terminals of themultiple piezoelectric elements Pzt in a constant state.

Meanwhile, in the head unit 3, the drive IC 50 includes a includes aselect control unit 510 and select units 520 which correspond to thepiezoelectric elements Pzt one to one. The select control unit 510controls selection of each of the select units 520. In detail, theselect control unit 510 stores the print data which is supplied incorrespondence with a clock signal from the control unit 110 in severalnozzles (piezoelectric elements Pzt) of the head unit 3 once, andinstructs each select unit 520 to select the drive signals COM-A andCOM-B in accordance with the print data at a start timing of a printperiod which is defined by a timing signal.

Each select unit 520 selects (or does not select any one) one of thedrive signals COM-A and COM-B in accordance with instruction of theselect control unit 510, and applies the selected signal to one terminalof the corresponding piezoelectric element Pzt as a drive signal of thevoltage Vout.

As described above, one piezoelectric element Pzt is provided in eachnozzle N in the actuator substrate 40. The other terminals of eachpiezoelectric element Pzt are coupled in common, and the voltage V_(BS)from the offset voltage generation circuit 130 is applied to the otherterminals through the wire 550.

In the present embodiment, ink is ejected from one nozzle N maximumtwice by one dot, and thus four gradations of a large dot, a medium dot,a small dot, and no record are represented. In the present embodiment,in order to represent the four gradations, two types of the drivesignals COM-A and COM-B are prepared, and each period has first halfpattern and a second half pattern. Then, during one period, the drivesignals COM-A and COM-B are selected (or not selected) in accordancewith a gradation to be represented in the first half and a second half,and the selected signal is supplied to the piezoelectric element Pzt.

Thus, the drive signals COM-A and COM-B will be first described, andthereafter, a detailed configuration of the select control unit 510 forselecting the drive signals COM-A and COM-B, and the select unit 520will be described.

FIG. 5 is a diagram illustrating waveforms or the like of drive signalsCOM-A and COM-B.

As illustrated in FIG. 5, the drive signal COM-A is configured by arepeated waveform of a trapezoidal waveform Adp1 which is disposedduring a period T1 from time when a control signal LAT is output (rises)to time when a control signal CH is output, during a print period Ta,and a trapezoidal waveform Adp2 which is disposed during a period T2from time when the control signal CH is output and to the control signalLAT is output during the print period Ta.

In the present embodiment, the trapezoidal waveforms Adp1 and Adp2 areapproximately the same waveforms as each ether, and are waveforms whicheject ink of a predetermined amount, specifically, an approximatelymedium amount from the nozzle N corresponding to the piezoelectricelements Pzt, if each waveform is supplied to the drive electrode 76which is one terminal of the piezoelectric elements Pzt.

The drive signal COM-B is configured by a repeated waveform of atrapezoidal waveform Bdp1 which is disposed during the period T1 and atrapezoidal waveform Bdp2 which is disposed during the period T2. In thepresent embodiment, the trapezoidal waveforms Bdp1 and Bdp2 arewaveforms different form each other. Among these, the trapezoidalwaveform Bdp1 is a waveform for preventing an increase of viscosity ofink by slightly vibrating the ink near the nozzle N. Accordingly, evenif the trapezoidal waveform Bdp1 is supplied to the one terminal of thepiezoelectric element Pzt, ink is not ejected from the nozzle Ncorresponding to the piezoelectric element Pzt. In addition, thetrapezoidal waveform Bdp2 is a waveform different from the trapezoidalwaveform Adp1 (Adp2). If the trapezoidal waveform Bdp2 is supplied tothe one terminal of the piezoelectric element Pzt, the trapezoidalwaveform Bdp2 becomes a waveform which ejects the amount of ink lessthan the predetermined amount from the nozzle N corresponding to thepiezoelectric element Pzt.

Voltages at a start timing of the trapezoidal waveforms Adp1, Adp2,Bdp1, and Bdp2, and voltages at an end timing of the trapezoidalwaveforms Adp1, Adp2, Bdp1, and Bdp2 are all common at a voltage Vcen.That is, the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 arewaveforms which respectively start at the voltage Vcen and ends at thevoltage Vcen.

In the present example, since the drive circuit 120 a (120 b)impedance-converts the signal Ain (Bin), a waveform of the signal Ain(Bin) which is input has some errors, but a waveform of the drive signalCOM-A (COM-B) is maintained as it is. Meanwhile, since the signal Ain(Bin) is obtained by amplifying a voltage of the signal ain (bin) by 10times, the waveform of the signal ain (bin) is 1/10 of the signal Ain(Bin). Since the signal ain (bin) is obtained by analog-converting thedata dA (dB), a voltage waveform of the drive signal COM-A (COM-B) isdefined by the control unit 110.

The control unit 110 outputs a signal OCa (select signal) having thefollowing logic level with respect to the trapezoidal waveform of thedrive signal COM-A (COM-B) to the drive circuit 120 a. In detail, thecontrol unit 110 causes the signal OCa to be in a High (H) level duringa period in which a voltage of the drive signal COM-A (signal Ain)decreases and a period in which the drive signal COM-A is constant at avoltage lower than a threshold value Vth1, and other than that, to be ina Low (L) level during a period in which the voltage of the drive signalCOM-A increases and a period in which the drive signal COM-A is constantat a voltage higher than the threshold value Vth1.

In the present example, when a maximum value of the voltage of the drivesignal COM-A (signal Ain) is referred to as max and a minimum valuethereof is referred to as min, description will be made by assuming thata relationship of max<Vth1<Vcen<min is satisfied for the sake ofconvenient. The relationship may be max<Vcen<Vth1<min. An example of thesignal OCa will be described below.

In the same manner, the control unit 110 outputs a signal OCb having thefollowing logic level with respect to the trapezoidal waveform of thedrive signal COM-B to the drive circuit 120 b. In detail, the controlunit 110 causes the signal OCb to be in a H level during a period inwhich a voltage of the drive signal COM-B (signal Bin) decreases and aperiod in which the drive signal COM-B is constant at a voltage lowerthan the threshold value Vth1, and other than that, to be in a L levelduring a period in which the voltage of the drive signal COM-B increasesand a period in which the drive signal COM-B is constant at a voltagehigher than or equal to the threshold value Vth1.

FIG. 6 is a diagram illustrating a configuration of the select controlunit 510 of FIG. 4.

As illustrated in FIG. 6, a clock signal Sck, the print data SI, and thecontrol signals LAT and CH are supplied to the select control unit 510.Multiple sets of a shift register (S/R) 512, a latch circuit 514, and adecoder 516 are provided in correspondence with each of thepiezoelectric elements Pzt (nozzles N) in the select control unit 510.

The print data SI is data which defines dots to be formed by all thenozzles N in the head unit 3 which is focused during the print periodTa. In the present embodiment, in order to represent the four gradationsof no record, a small dot, a medium dot, and a large dot, the print datafor one nozzle is configured by two bits of a most significant bit (MSB)and a least significant bit (LSB).

The print data SI is supplied in accordance with transport of the mediumP for each nozzle N (piezoelectric element Pzt) in synchronization withthe clock signal Sck. The shift register 512 has a configuration inwhich the print data SI of two bits is retained once in correspondencewith the nozzle N.

In detail, shift registers 512 of total m stages corresponding to eachof m piezoelectric elements Pzt (nozzles) are coupled in cascade, andthe print data SI which is supplied to the shift register 512 of a firststage located at a left end of FIG. 6 is sequentially transmitted to therear stage (downstream side) in accordance with the clock signal Sck.

In FIG. 6, in order to separate the shift registers 512, the shiftregister 512 are sequentially referred to as a first stage, a secondstage, . . . , an mth stage from the upstream side to which the printdata SI is supplied.

The latch circuit 514 latches the print data SI retained in the shiftregister 512 at a rising edge of the control signal LAT.

The decoder 515 decodes the print data SI of two bits which are latchedin the latch circuit 514, outputs select signals Sa and Sb for each ofperiods T1 and T2 which are defined by the control signal LAT and thecontrol signal CH, and defines selection of the select unit 520.

FIG. 7 is a diagram illustrating decoded content of the decoder 516.

In FIG. 7, the print data SI of two bits which are latched is referredto as an MSB and an LSB. In the decoder 516, if the latched print dataSI is (0,1), it means that logic levels of the select signals Sa and Sbare respectively output as levels of H and L during the period T1, andlevels of L and H during the period T2.

The logic levels of the select signals Sa and Sb are level-shifted by alevel shifter (not illustrated) to a higher amplitude logic than thelogic levels of the clock, signal Sck, the print data SI, and thecontrol signals LAT and CH.

FIG. 8 is a diagram illustrating a configuration of the select unit 520of FIG. 4.

As illustrated in FIG. 8, the select unit 520 includes inverters (NOTcircuit) 522 a and 522 b, and transfer gates 524 a and 524 b.

The select signal Sa from the decoder 516 is supplied to a positivecontrol terminal to which a round mark is not attached in the transfergate 524 a, is logically inverted by the inverter 522 a, and is suppliedto a negative control terminal to which a round mark is attached in thetransfer gate 524 a. In the same manner, the select signal Sb issupplied to a positive control terminal of the transfer gate 524 b, islogically inverted by the inverter 522 b, and is supplied to a negativecontrol terminal of the transfer gate 524 b.

The drive signal COM-A is supplied to an input terminal of the transfergate 524 a, and the drive signal COM-B is supplied to an input terminalof the transfer gate 524 b. The output terminals of the transfer gates524 a and 524 b are coupled to each other, and are coupled to oneterminal of the corresponding piezoelectric element Pzt.

If the select signal Sa is in a H level, the input terminal and theoutput terminal of the transfer gate 524 a are electrically coupled (ON)to each other. If the select signal Sa is in a L level, the inputterminal and the output terminal of the transfer gate 524 a areelectrically decoupled (OFF) from each other. In the same manner, theinput terminal and the output terminal of the transfer gate 524 b arealso electrically coupled to each other or decoupled from each other inaccordance with the select signal Sb.

As illustrated in FIG. 5, the print data SI is supplied to each nozzlein synchronization with the clock signal Sck, and is sequentiallytransmitted to the shift registers 512 corresponding to the nozzles.Thus, if supply of the clock signal Sck is stopped, the print data SIcorresponding to each nozzle is retained in each of the shift registers512.

If the control signal LAT rises, each of the latch circuits 514 latchesall of the print data SI retained in the shift registers 512. In FIG. 5,the number in L1, L2, . . . , Lm indicate the print data SI which islatched by the latch circuits 514 corresponding to the shift registers512 of the first stage, the second stage, the mth stage.

The decoder 516 outputs the logic levels of the select signals Sa and Sbin the content illustrated in FIG. 7 in accordance with the size of thedots which are defined by the latched print data SI during the periodsT1 and T2.

That is, first, the decoder 516 sets the select signals Sa and Sb tolevels of H and L during the period T1 and levels of H and L even duringthe period T2, if the print data SI is (1,1) and the size of the largedot is defined. Second, the decoder 516 sets the select signals Sa andSb to levels of H and L during the period T1 and levels of L and Hduring the period T2, if the print data SI is (0,1) and the size of themedium dot is defined. Third, the decoder 516 sets the select signals Saand Sb to levels of L and L during the period T1 and levels of L and Hduring the period T2, if the print data SI is (1,0) and the size of thesmall dot is defined. Fourth, the decoder 516 sets the select signals Saand Sb to levels of L and H during the period T1 and levels of L and Lduring the period T2, if the print data SI is (0,0) and no recode isdefined.

FIG. 9 is a diagram illustrating waveforms of the drive signals whichare selected in accordance with the print data SI and are supplied toone terminal of the piezoelectric element Pzt.

When the print data SI is (1,1), the select signals Sa and Sb become Hand L levels during the period T1, and thus the transfer gate 524 a isturned on, and the transfer gate 524 b is turned off. Accordingly, thetrapezoidal waveform Adp1 of the drive signal COM-A is selected duringthe period T1. Since the select signals Sa and Sb are in H and L levelseven during the period T2, the select unit 520 selects the trapezoidalwaveform Adp2 of the drive signal COM-A.

In this way, if the trapezoidal waveform Adp1 is selected during theperiod T1, the trapezoidal waveform Adp2 is selected during the periodT2, and the selected waveforms are supplied to one terminal of thepiezoelectric element Pzt as drive signals, ink of an approximatelymedium amount is ejected twice from the nozzle N corresponding to thepiezoelectric element Pzt. Accordingly, each ink is landed on andcombined with the medium P, and as a result, a large dot is formed asdefined by the print data SI.

When the print data SI is (0,1), the select signals Sa and Sb become Hand L levels during the period T1, and thus the transfer gate 524 a isturned on, and the transfer gate 524 b is turned off. Accordingly, thetrapezoidal waveform Adp1 of the drive signal COM-A is selected duringthe period T1. Next, since the select signals Sa and Sb are in L and Hlevels during the period T2, the trapezoidal waveform Bdp2 of the drivesignal COM-B is selected.

Hence, ink of an approximately medium amount and an approximately smallamount is ejected twice from the nozzle N. Accordingly, each ink islanded on and combined with the medium P, and as a result, a medium dotis formed as defined by the print data SI.

When the print data SI is (1,0), the select signals Sa and Sb become allL levels during the period T1, and thus the transfer gates 524 a and 524b are turned off. Accordingly, the trapezoidal waveforms Adp1 and Bdp1are not selected during the period T1. If the transfer gates 524 a and524 b are all turned off, a path from a coupling point of the outputterminals of the transfer gates 524 a and 524 b to one terminal of thepiezoelectric element Pzt becomes a high impedance state in which thepath is not electrically coupled to any portion. However, both terminalsof the piezoelectric element Pzt retain a voltage (Vcen-V_(BS)) shortlybefore the transfer gates are turned off, by capacitance included in thepiezoelectric element Pzt itself.

Next, since the select signals Sa and Sb are in L and H levels duringthe period T2, the trapezoidal waveform Bdp2 of the drive signal COM-Bis selected. Accordingly, ink of an approximately small amount isejected from the nozzle N only during the period T2, and thus small dotis formed on the medium P as defined by the print data SI.

When the print data SI is (0,0), the select signals Sa and Sb become Land H levels during the period T1, and thus the transfer gates 524 a isturned off and the transfer gate 524 b is turned on. Accordingly, thetrapezoidal waveforms Bdp1 of the drive signal COM-B is selected duringthe period T1. Next, since all of the select signals Sa and Sb are in Llevels during the period T2, the trapezoidal waveforms Adp2 and Bdp2 areall not selected.

Accordingly, ink near the nozzle N just slightly vibrates during theperiod T1, and the ink is not ejected, and thus, as a result, dots arenot formed, that is, no record is made as defined by the print data SI.

In this way, the select unit 520 selects (or does not select) the drivesignals COM-A and COM-B in accordance with instruction of the selectcontrol unit 510, and applies the selected signal to one terminal of thepiezoelectric element Pzt. Accordingly, each of the piezoelectricelements Pzt is driven in accordance with the size of the dot which isdefined by the print data SI.

The drive signals COM-A and COM-B illustrated in FIG. 5 are just anexample. Actually, combinations of various waveforms which are preparedin advance are used in accordance with properties, transport speed, orthe like of the medium P.

In addition, here, an example in which the piezoelectric element Pzt isbent upwardly in accordance with a decrease of a voltage is used, but ifa voltage which is applied to the drive electrodes 72 and 76 isinverted, the piezoelectric element Pzt is bent downwardly in accordancewith a decrease of the voltage. Accordingly, in a configuration in whichthe piezoelectric element Pzt is bent downwardly in accordance with adecrease of a voltage, the drive signals COM-A and COM-B illustrated inthe figure have waveforms which are inverted by using the voltage Vcenas a reference.

Next, the drive circuit 120 a and 120 b of the main substrate 100 willbe described.

In relation to symbols of the drive circuits, a symbol of a side onwhich the drive signal COM-A is output is unified as 120 a, and a symbolof a side on which the drive signal COM-B is output is unified as 120 b,but since there are several aspects as will be describe below, there isa case where parenthesis such as a drive circuit (Example 1) or a drivecircuit (Example 2) is attached instead of a symbol so that each of themis distinguished in the same manner as in the printing apparatus.

Hence, in relation to the drive circuit (Example 1), the drive circuit120 a on a side on which the drive signal COM-A (COM-B) is output willbe first described as an example.

FIG. 10 is a diagram illustrating the drive circuit (Example 1). Asillustrated in this figure, the drive circuit 120 a includesdifferential amplifiers 221 and 225, a selector 223, a pulse inserter227, transistors 231 and 232, resistance elements Ru and Rd, and acapacitor C0.

A voltage of the signal Ain which is an input of the drive circuit 120 ais referred to as Vin, and a voltage of the node N2 which is an outputis referred to as Out.

A negative input terminal (−) of the differential amplifier 221 receivesthe signal Ain, and the drive signal COM-A which is an output is fedback to a positive input terminal (+) of the differential amplifier 221.Accordingly, the differential amplifier 221 outputs a difference voltagewhich is obtained by subtracting a voltage of the negative inputterminal (−) from a voltage of the positive input terminal (+), that is,a difference voltage which is obtained by subtracting a voltage Vin ofthe signal Ain (source drive signal) with a large amplitude that is aninput from a voltage Out, which will be described below, of the drivesignal COM-A which is an output, and outputs the amplified voltage.

However, for example, the differential amplifier 221 uses a highpotential side of a power supply as a voltage V_(D), and uses a lowpotential side thereof as a ground Gnd, while not particularlyillustrated. Accordingly, an output voltage is within a range from theground Gnd to the voltage V_(D).

There a case where an output signal of the differential amplifier 221 isalso used as a signal for a switching operation which will be describedbelow, but is also used as a signal for a linear operation. In a casewhere the output signal is used as the signal for the switchingoperation, a H level indicates the voltage V_(D), and a L levelindicates the ground Gnd of a zero voltage. In addition, since theoutput signal of the differential amplifier 221 controls switchingoperations and linear operations of transistors 231 and 232 after all aswill be described below, the output signal can be said to be a controlsignal for the transistors.

There is also a case where a voltage of a drive signal is decreased andfed back and a source drive signal is voltage-amplified to output as thedrive signal, and thus, it may be said that a signal based on the drivesignal is fed back to the differential amplifier 221.

In the same manner as the differential amplifier 221, a negative inputterminal (−) of the differential amplifier 225 receives the signal Ain,and the drive signal COM-A which is an output feeds back to a positiveinput terminal (+) of the differential amplifier 225. However, ahigh-side power supply voltage of the differential amplifier 225 isvoltage V_(D) in common, but a low-side power supply voltage thereof is,for example, a voltage −V_(D) lower than the ground Gnd. Accordingly,the differential amplifier 225 outputs a difference voltage which isobtained by subtracting the voltage Vin from the voltage Out as apositive voltage higher than the ground Gnd if the voltage Out of thedrive signal COM-A is higher than the voltage Vin of the signal Ain, andoutputs the difference voltage as a negative voltage lower than theground Gnd if the voltage Out is lower than the voltage Vin.

Anyway, a voltage of a signal which is output from the differentialamplifier 225 indicates a difference between the voltage Vin and thevoltage Out, in view of an absolute value which uses the ground Gnd as areference.

If the voltage of the signal which is output from the differentialamplifier 225 is higher than or equal to a threshold value Vth2 as anabsolute value, the pulse inserter 227 inverts a logic level of thesignal OCa at the time for a predetermined time to output as a signalODa. That is, if a difference between the voltage Vin and the voltageOut is larger than or equal to the threshold value Vth2 as an absolutevalue, the pulse inserter 227 inserts a pulse into the signal OCa tooutput as the signal ODa.

If the signal ODa is in a L level, the selector (select unit) 223selects the output signal of the differential amplifier 221 as a signalGt1, supplies the selected signal to a gate terminal of a transistor231, selects a L level as a signal Gt2, and supplies the selected Llevel to a gate terminal of a transistor 232. Meanwhile, if the signalODa is in a H level, the selector 223 selects a H level as the signalGt1, supplies the selected H level to the gate terminal of thetransistor 231, selects the output signal of the differential amplifier221 as the signal Gt2, and supplies the selected output signal to thegate terminal of the transistor 232.

In other words, there is provided a configuration in which, if thesignal ODa is in a L level, the selector 223 selects the transistor 231and supplies a difference signal which is the output signal of thedifferential amplifier 221 to the gate terminal of the transistor 231,and if the signal ODa is in a H level, the selector 223 selects thetransistor 232, supplies the difference signal to the gate terminal ofthe transistor 232, and supplies a signal which turns off the transistorto the gate terminal of the unselected transistor as will be describedbelow.

The pair of transistors are configured by transistors 231 and 232. Thetransistor 231 (high-side transistor) on a high side of these is, forexample, a P-channel field effect transistor, and a high-side voltageV_(D) is applied to a source terminal thereof. The transistor 232(low-side transistor) on a low side is, for example, an N-channel fieldeffect transistor, and a source terminal thereof is coupled to theground Gnd which is a low side of the power supply.

Drain terminals of the transistors 231 and 232 are coupled to eachother, and become a node N2 which is the output terminal of the drivecircuit 120 a. That is, the drive signal COM-A is configured to outputfrom the node N2.

The node N2 is coupled to the positive input terminal (+) of thedifferential amplifier 221, and voltage of the node is pulled up to thevoltage V_(D) through the resistance element Ru (first resistanceelement), while being pulled down to the ground through the resistanceelement Ed (second resistance element). In addition, the capacitor C0(output capacitor) is provided to prevent abnormal oscillation fromoccurring, one terminal thereof is coupled to the node N2, and the otherterminal thereof is coupled to a constant potential, for example, theground Gnd.

Here, the drive circuit 120 a which outputs the drive signal COM-A willbe described, but a configuration of the drive circuit 120 b whichoutputs the drive signal COM-B is the same as the configuration of thedrive circuit 120 a, and only the input and output signals are differentfrom each other. That is, in the drive circuit 120 b which is denoted bya parenthesis of FIG. 10, the negative input terminal (−) of thedifferential amplifier 221 receives the signal Bin and the selector 223receives the signal OCb, while the drive signal COM-B is output from thenode N2.

Next, a configuration of a drive circuit according to a comparativeexample will be described before an operations of the drive circuits 120a and 120 b will be described.

FIG. 17 is a diagram illustrating the configuration of the drive circuitaccording to the comparative example. A difference between the drivecircuit (comparative example) illustrated in this figure and the drivecircuit (Example 1) illustrated in FIG. 10 is that the drive circuit(comparative example) does not include the differential amplifier 225and the pulse inserter 227 and the signal OCa (OCb) is directly coupledto the selector 223.

An operation of the drive circuit (comparative example) will bedescribed by using a side from which the drive signal COM-A is output asan example.

FIG. 18 is a diagram illustrating the operation of the drive circuit(comparative example).

In this figure, the signal Ain is a signal into which the drive signalCOM-A is not impedance-converted, thus, thereby, having approximatelythe same waveform as the drive signal COM-A. In addition, as describedabove, the drive signal COM-A has a waveform in which two trapezoidalwaveforms Adp1 and Adp2 which are the same are repeated during a printperiod Ta, and thus, the signal Ain also has the same waveform which isrepeated.

FIG. 18 illustrates one trapezoidal waveform of the repeating waveforms.In addition, in the figure, a period P1 is a period in which the voltageVin of the signal Ain decreases from the voltage Vcen to the minimumvalue min, a period P2 subsequent to the period P1 is a period in whichthe voltage Vin is constant at the minimum value min, a period P3subsequent to the period P2 is a period in which the voltage Vinincreases from the minimum value min to the maximum value, a period P4subsequent to the period P3 is a period in which the voltage Vin isconstant at the maximum value max, and a period P5 subsequent to theperiod P4 is a period in which the voltage Vin decreases from themaximum value max to the voltage Vcen.

A vertical scale denoting a voltage with respect to each voltagewaveform of FIG. 18 is not necessarily assigned for the sake ofconvenient description.

First, the period P1 is a voltage decrease period of the drive signalCOM-A (Ain). Accordingly, since the signal OCa is in a H level duringthe period P1, the selector 223 selects a H level as the signal Gt1, andselects the output signal of the differential amplifier 221 as thesignal Gt2.

Since the signal Gt1 is in a H level during the period P1, the P-channeltransistor 231 is turned off.

Meanwhile, first, the voltage Vin of the signal Ain decreases ahead ofthe voltage Out of the node N2 during the period P1. In other words, thevoltage Out becomes a voltage higher than or equal to the voltage Vin.Accordingly, a voltage of the output signal of the differentialamplifier 221 which selected as the signal Gt2 increases in accordancewith the difference voltage between two voltages, and swings to a Hlevel. If the signal Gt2 is in a H level, the transistor 232 is turnedon, and thus, the voltage Out decreases. Actually, the voltage Out isnot decreased to the ground Gnd immediately, and is decreased slowly intime integration by the capacitor C0, the piezoelectric element Pzt withcapacitance, or the like.

If the voltage Out decreases to be lower than the voltage Vin, thesignal Gt2 is in a L level, and the transistor 232 is turned off, butsince the voltage Vin is low, the voltage Out increases to be higherthan or equal to the voltage Vin again. Accordingly, the signal Gt2 isin a H level, and thereby, the transistor 232 is turned on again.

During the period P1, the signal Gt2 is alternately switched between a Hlevel and a L level, and thereby, the transistor 232 performs anoperation of repeating turn-on and turn-off, that is, a switchingoperation. By the switching operation, control of causing the voltageOut to follow a decrease of the voltage Vin is performed.

Next, the period P2 is a period in which the drive signal COM-A (Ain) isconstant at the minimum value min of a voltage lower than the thresholdvoltage Vth1. Accordingly, the signal OCa is in a H level subsequent tothe period P1 during the period P2, and thus, the selector 223 selects aH level as the signal Gt1 and selects the output signal of thedifferential amplifier 221 as the signal Gt2.

The voltage Out is controlled to follow the voltage Vin during theperiod P1, but content of the control is the switching operation of thetransistor 232 as described above. Accordingly, there is a case where,shortly after the period P2 starts, that is, shortly after the voltageVin turns to be constant at the minimum value min, the voltage Out doesnot coincide with the voltage Vin.

In this case, if the voltage Out is higher than the voltage Vin, thevoltage of the signal Gt2, that is, the output voltage of thedifferential amplifier 221 also increases, and thus, resistance betweena source and a drain of the transistor 232 decreases, thereby,decreasing the voltage Out of the node N2. Meanwhile, if the voltage Outis lower than the voltage Vin, the voltage of the signal Gt2 alsodecreases, and thus, the resistance between the source and the drain ofthe transistor 232 increases, thereby, increasing the voltage Out.

Hence, during the period P2, the voltage Out becomes constant at a pointwhere a direction in which the voltage Out decreases and a direction inwhich the voltage increases balance each other, that is, a point wherethe voltage Out coincides with the voltage Vin (minimum value min). Atthis time, the transistor 232 performs a linear operation, and thesignal Gt2 is constant at a voltage in which the voltage Out that isdetermined by the resistance between the source and the drain of thetransistor 232 and the resistance elements Ru and Rd becomes the voltageVin.

FIG. 18 illustrates a state where the voltage of the signal Gt2 changesbriefly from the period P1 to the period P2 thereby becoming immediatelyconstant.

The period P3 is a voltage increase period of the drive signal COM-A(Ain). Accordingly, the signal OCa is in a L level during the period P3,and thus, the selector 223 selects the output signal of the differentialamplifier 221 as the signal Gt1, and selects a L level as the signalGt2.

The signal Gt2 is in a L level during the period P3, and thus, theN-channel transistor 232 is turned off.

Meanwhile, first, the voltage Vin increases ahead of the voltage Outduring the period P3. In other words, the voltage Out decreases to belower than the voltage Vin. Accordingly, the voltage of the outputsignal of the differential amplifier 221 which is selected as the signalGt1 decreases in accordance with the difference voltage between twovoltages, and approximately swings to a L level. If the signal Gt1 is ina L level, the transistor 231 is turned on, and thus, the voltage Outincreases. Actually, the voltage Out is not increased to the voltageV_(D) immediately, and is increased slowly in time integration by thecapacitor C0, the piezoelectric element Pzt with capacitance, or thelike.

If the voltage Out is in a voltage higher than or equal to the voltageVin, the signal Gt2 is in a H level, and the transistor 231 is turnedoff. If the transistor 231 is turned off, an increase of the voltage outis stopped, but since the voltage Vin increases, the voltage Outdecreases to be lower than the voltage Vin again. Accordingly, thesignal Gt1 is in a L level, and the transistor 231 is turned on again.

The signal Gt1 is alternately switched between a K level and a L levelduring the period P3, and thereby, the transistor 231 performs aswitching operation. By the switching operation, control of causing thevoltage Out to follow an increase of the voltage Vin is performed.

The period P4 is a period in which the drive signal COM-A (Ain) isconstant at a voltage higher than or equal to the threshold voltageVth1. Accordingly, during the period P2, the signal OCa is in a L levelsubsequent to the period P3, and thus, the selector 223 selects theoutput signal of the differential amplifier 221 as the signal Gt1, andselects a L level as the signal Gt2.

The voltage Out is controlled to follow the voltage Vin during theperiod P3, but content of the control is the switching operation of thetransistor 231 as described above, and thus, there is a case where,shortly after the voltage Vin turns to be constant at the maximum valuemax during the period P4, the voltage Out does not coincide with thevoltage Vin of the signal Ain.

In this case, if the voltage Out is higher than the voltage Vin, thevoltage of the signal Gt1, that is, the output voltage of thedifferential amplifier 221 also increases, and thus, resistance betweena source and a drain of the transistor 231 increases, thereby,decreasing the voltage Out of the node N2. Meanwhile, if the voltage Outis lower than the voltage Vin, the voltage of the signal Gt1 alsodecreases, and thus, the resistance between the source and the drain ofthe transistor 231 decreases, thereby, increasing the voltage Out.

Hence, during the period P4, the voltage Out becomes constant at a pointwhere a direction in which the voltage Out decreases and a direction inwhich the voltage increases balance each other, that is, a point wherethe voltage Out coincides with the voltage Vin (maximum value max). Atthis time, the transistor 232 performs a linear operation, and thesignal Gt2 is constant at a voltage in which the voltage Out that isdetermined by the resistance between the source and the drain of thetransistor 232 and the resistance elements Ru and Rd becomes the voltageVin (maximum value max).

FIG. 18 illustrates a state where the voltage of the signal Gt2 changesbriefly from the period P3 to the period P4 thereby becoming immediatelyconstant.

The period P5 is a voltage decrease period of the drive signal COM-A(Ain). Accordingly, an operation in the period P5 is the same as in theperiod P1. That is, the signal Gt2 is alternately switched between a Hlevel and a L level, and thereby, the transistor 232 performs aswitching operation, and control of causing the voltage Out of the nodeN2 to follow a decrease of the voltage Vin is performed. In relation tothe period P4, the signal OCa is switched to a H level during the periodP5, and thus, the selector 223 selects a H level as the signal Gt1, andselects the output signal of the differential amplifier 221 as thesignal Gt2.

A period P6 subsequent to the period P5 is a period in which the drivesignal COM-A (Ain) is constant at the voltage Vcen lower than thethreshold voltage Vth1. Accordingly, the signal OCa is in a H levelsubsequent to the period P5 during the period P6, and thus, the selector223 selects a H level as the signal Gt1 and selects the output signal ofthe differential amplifier 221 as the signal Gt2.

The control of causing the voltage Out to follow the voltage Vin of thesignal Ain is performed during the period P5, but there is a case where,shortly after the voltage Vin turns to be constant at the voltage Vcenduring the period P6, the voltage Out does not coincide with the voltageVin of the signal Ain. However, the voltage Out is constant at a pointin which the voltage coincides with the voltage Vin (Vcen), in the samemanner shortly after being turned to the period P2. At this time, thetransistor 232 performs a linear operation, and the signal Gt2 isconstant at a voltage, in which the voltage Out that is determined bythe resistance between the source and the drain of the transistor 232and the resistance elements Ru and Rd becomes the voltage Vin (Vcen).

FIG. 18 illustrates a state where the voltage of the signal. Gt2 changesbriefly from the period P5 to the period P6 thereby being immediatelybalanced.

According to the drive circuit (comparative example) illustrated in FIG.17, the control of causing the voltage Out of the drive signal COM-A tofollow the voltage Vin of the signal Ain is performed by the followingoperation for each of the periods P1 to P6.

That is, the controls of causing the voltage Out to follow the voltageVin are performed, by the switching operation of the transistor 232during the periods P1 and P5 in which the voltage Vin decreases, by thelinear operation of the transistor 232 during the period P2 and P6 inwhich the voltage Vin is constant at a value lower than the thresholdvoltage Vth1, by the switching operation of the transistor 231 duringthe period P3 in which the voltage Vin increases, and by the linearoperation of the transistor 231 during the period P4 in which thevoltage Vin is constant at a value higher than the threshold voltageVth1, respectively.

Description is made in which, in the drive circuit (comparativeexample), the transistor 231 performs a switching operation during theperiod P3 in which the output voltage VOUT (the voltage Vin of thesignal Ain) of the drive signal COM-A increases, and the transistor 232performs a switching operation during the periods P1 and P5 in which theoutput voltage VOUT decreases, but in a case where the number ofpiezoelectric elements Pzt to be coupled is large, a linear operationcan also be performed in a relationship of a time constant which isdetermined by ON-resistance of a transistor and a load capacitance.

In addition, description is made in which, in the drive circuit(comparative example), the transistor 231 performs a linear operationduring the period P4 in which the voltage Vout is constant at a voltagehigher than or equal to the threshold voltage Vth1, and the transistor232 performs a linear operation during the periods P2 and P6 in whichthe voltage Vout is constant at a voltage lower than the thresholdvoltage Vth1, but a switching operation can also be performed by thesame reason.

According to the drive circuit (comparative example), transistors 231and 232 do not perform a switching operation during the periods P2, P4,and P6 in which the voltage Vin is constant, compared with the class Damplification in which switching is continuously performed. In addition,in the class D amplification, a low pass filter (LPF) for demodulating aswitching signal, particularly, an inductor such as a coil is needed,but in the drive circuit (comparative example), the LPF is not needed.Accordingly, according to the class D amplification, it is possible toreduce power which is consumed by a switching operation or the LPF, andalso to simplify and minimize a circuit, compared with the drive circuit(comparative example).

In this way, the drive circuit (comparative example) has many excellentpoints, compared with the class D amplification, but the followingproblems are pointed out. As described above, the control of causing thevoltage Out of the drive signal COM-A to follow the voltage Vin of thesignal Ain is performed basically by the switching operations of thetransistors 231 and 232 during the voltage increase period or thevoltage decrease period, and is performed by the linear operation of thetransistors 231 and 232 during the voltage-constant period. Accordingly,when the switching operation is changed to the linear operation, thatis, when the voltage increase period or the voltage decrease period ischanged to the voltage-constant period, deviation of the voltage Outwith respect to the voltage Vin can increase.

FIG. 19 is a diagram illustrating an example in which the deviation ofthe voltage Out with respect to the voltage Vin increase. FIG. 18illustrates a part surrounded by a dashed line Bt, that is, an enlargedwaveform or the like of the drive signal COM-A when the period P1 ischanged to the period P2.

In this figure, a thin line indicates a waveform of the signal Ain(voltage Vin) which is an input, and a bold line indicates a waveform ofthe drive signal COM-A (voltage Out) which is an output. This figureillustrates an example in which, as the voltage Vin of the signal Aindecreases, the voltage Out of the drive signal COM-A is decreased by aswitching operation, but when the voltage Vin is constant, the deviationof the voltage Out with respect to the voltage Vin increases.

The example of FIG. 19 illustrates a case where the voltage Vin changesfrom a decreasing state to a constant state, but the same problem canoccur even in a case where the voltage Vin changes from an increasingstate to a constant state. However, the P-channel transistor 231 whichincreases the voltage Out has a slower response than the N-channeltransistor 232 in general, and thus, it is considered that a possibilitythat deviation is increased by overshoot shortly after the switchingoperation ends is low.

In contrast to the drive circuit (comparative example), the drivecircuit (Example 1) according to the present embodiment includes thedifferential amplifier 225 and the pulse inserter 227 which areillustrated in FIG. 10.

FIG. 11 is a diagram illustrating an operation of the drive circuit(Example 1), and illustrates a state where, in a case where the voltageVin of the signal Ain changes from a decreasing state to a constantstate, when deviation of the voltage Out with respect to the voltage Vinis higher than or equal to the threshold value Vth2 in view of anabsolute value, the pulse inserter 227 inserts the pulse Pls with awidth of a period Pd into the signal OCa to output as the signal ODa.

The transistor 232 is forcibly turned off and the transistor 231 isforcibly turned on by the pulse Pls, and thus, the voltage Out of thedrive signal COM-A increases so as to remove the deviation. After thevoltage Out is increased by the pulse Pls, the voltage Out follows thevoltage Vin by aforementioned switching operation.

In FIG. 11, a case where the voltage Vin changes from a decreasing stateto a constant state is used as an example, but deviation may increaseeven in a case where the voltage Vin changes from an increasing state toa constant state in the same manner.

In a case where the voltage Vin changes from an increasing state to aconstant state, when deviation of the voltage Out with respect to thevoltage Vin is higher than or equal to the threshold value Vth2 in viewof an absolute value, the pulse inserter 227 inserts the pulse Pls intothe signal OCa with a L level to output as the signal ODa, while notillustrated in particular, and thus, the transistor 231 is forciblyturned off and the transistor 232 is forcibly turned on. Thereby, thevoltage Out of the drive signal COM-A decreases to remove the deviation.After the voltage Out decreases, the voltage Out follows the voltage Vinby aforementioned linear operation.

Hence, according to the drive circuit (Example 1), deviation of thedrive signal COM-A with respect to the signal Ain which is an input,particularly, deviation occurring when a voltage with a trapezoidalwaveform changes from a decreasing state or an increasing state to aconstant state is reduced, and thus, waveform reproducibility isimproved. Accordingly, accuracy of ink ejection increases, and as aresult, it is possible to obtain results of high quality print.

The drive signal COM-A (COM-B) is not limited to a trapezoidal waveform,and may be a waveform with continuous slope, such as a sine wave. In thedrive circuit (Example 1), in a case where the waveform is output, if achange of the voltage Vout (voltage Vin of the signal Ain) of the drivesignal COM-A is relatively large, specifically, one of the transistors231 and 232 performs a switching operation during a period in which avoltage changes to a predetermined voltage or higher on a per unit timebasis. Meanwhile, if the change of the voltage Vout is relatively small,specifically, one of the transistors 231 and 232 performs a linearoperation during a period (second period) in which the voltage changesto a voltage lower than the predetermined voltage on a per unit timebasis or the voltage is constant without a change.

In addition, in the drive circuit (Example 1), a destination of pull-upof the resistance element Ru may be a voltage higher than or equal to amaximum voltage of the drive signal COM-A, and thus, the destination isa power supplying line of the voltage V_(D) in this example. Inaddition, a destination of pull-down of the resistance element Rd may bea voltage lower than or equal to a minimum voltage of the drive signalCOM-A, and thus, the destination is the ground Gnd in this example.

Here, the drive circuit 120 a which outputs the drive signal COM-A isdescribed as an example, but the drive circuit 120 b which outputs thedrive signal COM-B also performs the same operation. A waveform of thedrive signal COM-B is the same as the waveform illustrated in FIG. 5,the signal OCb is the same as described above, and thus, a waveformthereof is not illustrated. The drive circuit 120 b also outputs thedrive signal COM-B of the voltage Vout following the voltage of thesignal Bin.

However, in the configuration illustrated in FIG. 10, the resistanceelements Ru and Rd are coupled electrically and directly between thevoltage V_(D) of the power supply and the ground Gnd, and thus, athrough-current continuously flows, and there is room for reducing powerconsumption. Hence, next, a drive circuit (Example 2) having a differentconfiguration whose power consumption is reduced will be described.

FIG. 12 is a diagram illustrating a configuration of the drive circuit(Example 2). The drive circuit (Example 2) illustrated in the figure isdifferent from the drive circuit (Example 1) illustrated in FIG. 10 inthat the drive circuit (Example 2) includes a switch Swu. The switch Swuis electrically coupled to the resistance element Ru in series betweenthe power supplying line of the voltage V_(D) on a high side of thepower supply voltage and the node N2, is turned on if the signal OCa isin a H level, and is turned off if the signal OCa is in a L level.Accordingly, in a case where the output signal of the differentialamplifier 221 is selected by the selector 223 as the signal Gt1, thatis, during the periods P1, P2, P5, and P6, the switch Swu is turned on.Meanwhile, in a case where the output signal of the differentialamplifier 221 is selected as the signal Gt2, that is, during the periodsP3 and P4, the switch Swu is turned off. Accordingly, the drive circuit(Example 2) can reduce power which is consumed by the through-current,compared with the drive circuit (Example 1) illustrated in FIG. 10.

In the drive circuit (Example 2), the switch Swu is provided on a sideof the resistance element Ru for pull-up, but a configuration in whichanother switch is provided on a side of the resistance element Rd forpull-down may be provided, in the configuration, the switch may beturned on when the signal OCa is in a L level, and may be turned offwhen the signal OCa is in a H level, in addition, as will be describedbelow, ON and OFF of the switch on a pull-up side may be controlleddifferently from ON and OFF of the switch on a pull-down side.

Here, functions of pull-up and pull-down of the node N2 will bedescribed.

A case where pull-up is required is a case where the transistor 232performs a linear operation during the periods P2 and P6 in which thesignal Ain (the drive signal COM-A) is constant at a voltage lower thanthe threshold value Vth1. In this case, the transistor 231 on a highside is turned off, and thus, it is necessary for the node N2 to bepulled up on a high side such that the voltage Out of the node N2follows the signal Ain by the transistor 232. In other words, the switchSwu may be in a state of being turned on during the periods P2 and P6.

Meanwhile, a case where pull-down is required is a case where thetransistor 231 performs a linear operation during the period P4 in whichthe signal Ain (the drive signal COM-A) is constant at a voltage higherthan the threshold value Vth1. In this case, the transistor 232 on a lowside is turned off, and thus, it is necessary for the node N2 to bepulled down on a low side such that the voltage Out of the node N2follows the signal Ain by the transistor 231. The switch provided on thepull-down side may be in a state of being turned on during the periodP4.

Hence, in the drive circuit (Example 1), the transistor 231 or 232 isturned on by the pulse Pls so as to reduce deviation of the voltage Outwith respect to the voltage Vin, but a configuration in which thedeviation is reduced can also be used for the following drive circuit(Example 3).

Accordingly, the drive circuit (Example 4) will be describedhereinafter.

FIG. 13 is a block diagram illustrating an electrical configuration of aprinting apparatus (Example 2) including the drive circuit (Example 3).A difference between the printing apparatus (Example 2) illustrated inthis figure and the printing apparatus (Example 1) illustrated in FIG. 4is that the control unit 110 supplies a signal VRa to the drive circuit120 a and supplies a signal VRb to the drive circuit 120 b.

In this example, the control unit 110 outputs the signals VRa and VRb,each having a H level.

FIG. 14 is a diagram illustrating a configuration of the drive circuit(Example 3). A difference between the drive circuit (Example 3)illustrated in this figure and the drive circuit (Example 1) illustratedin FIG. 10 is first that the resistance element Ru is replaced with avariable resistor.

In this example, the resistance element Ru can be switched by two levelsof a high level and low level, and in detail, the resistance element Ruis set to have high resistance if a signal VSa is in a H level, and isset to have low resistance if the signal VSa is in a L level.

In addition, in the drive circuit (Example 3), the pulse inserter 227 isprovided on a side on which the signal VRa is supplied from the controlunit 110. In detail, if a voltage of a signal which is output from thedifferential amplifier 225 is higher than or equal to the thresholdvalue Vth2, the pulse inserter 227 inverts a logic level of the signalVRa at that time for a predetermined time to output as the signal VSa.That is, if a difference between the voltage Vin and the voltage Out islarger than or equal to the threshold value Vth2, the pulse inserter 227inserts a pulse into the signal VRa to output as the signal VSa.

FIG. 15 is a diagram illustrating an operation of the drive circuit(Example 3). In this figure, the pulse Pls is inserted into the signalVRa by the pulse inserter 227 at a next location U1.

That is, the location U1 is a point in which deviation of the voltageOut with respect to the voltage Vin is higher than or equal to thethreshold value Vth2 in view of an absolute value, after the voltage Vinof the signal Ain changes from a decreasing state to a constant state.

The signal VSa is changed to a L level by the pulse Pls at the locationU1, and thereby, a resistance value of the resistance element Ru isreduced, pull-up of the node N2 increases, the voltage Out increases,and deviation of the voltage Out with respect to the voltage Vin isreduced in the same manner as the drive circuit (Example 1).

After the voltage Vin of the signal Ain changes from the increasingstate to the constant state, the deviation of the voltage Out withrespect to the voltage Vin can also be higher than or equal to thethreshold value Vth2 in view of an absolute value. However, as describedabove, the P-channel transistor 231 has a relatively slow response, andthus, it is considered that a possibility that the deviation isincreased by overshoot shortly after the switching operation ends islow, but in order to reduce the deviation, for example, the followingconfiguration may be provided.

That is, a configuration may be provided in which the resistance elementRd on a pull-down side is replaced with a variable resistor andresistance of the resistance element Rd is reduced to decrease thevoltage Out when the deviation of the voltage Out with respect to thevoltage Vin is higher than or equal to the threshold value Vth2 in viewof an absolute value during a period in which the transistor 231 isactivated (that is, a period in which the signal OCa is in a L level).

In the configuration, in relation to the resistance element Ru on apull-up side, resistance of the resistance element Ru is reduced toincrease the voltage Out when the deviation of the voltage Out withrespect to the voltage Vin is higher than or equal to the thresholdvalue Vth2 in view of an absolute value during a period in which thetransistor 232 is activated (that is, a period in which the signal OCais in a H level).

Here, the drive circuit 120 a which outputs the drive signal COM-A willbe described, but a configuration of the drive circuit 120 b whichoutputs the drive signal COM-B is the same as the drive circuit 120 a,and only an input signal is different from each other. That is, in thedrive circuit 120 b, an input of the pulse inserter 227 becomes thesignal VRb and an output thereof becomes VSb, as denoted by parenthesisof FIG. 14.

The drive circuit (Example 3) may also include a switch which prevents athrough-current from continuously flowing. Hence, the drive circuit(Example 4) which is configured by adding the switch to the drivecircuit (Example 3) will be described hereinafter.

FIG. 16 is a diagram illustrating a configuration of the drive circuit(Example 4).

A difference between the drive circuit (Example 4) illustrated in thisfigure and the drive circuit (Example 3) illustrated in FIG. 14 is thatthe drive circuit (Example 4) includes the switch Swu. The switch Swu isthe same manner as in the drive circuit (Example 2), and is turned on ina case where the output signal of the differential amplifier 221 isselected by the selector 223 as the signal Gt1, that is, during theperiods P1, P2, P5, and P6. Meanwhile, the switch Swu is turned off in acase where the output signal of the differential amplifier 221 isselected as the signal Gt2, that is, during the periods P3 and P4.Accordingly, according to the drive circuit (Example 4), power which isconsumed by a through-current can be further reduced, compared with thedrive circuit (Example 3) illustrated in FIG. 14.

In the drive circuit (Example 4), a configuration in which anotherswitch is provided on a side of the resistance element Rd for pull-downmay be provided. In the configuration, the switch may be turned on whenthe signal OCa is in a L level, and may be turned off when the signalOCa is in a H level. In addition, ON and OFF of the switch on a pull-upside may be controlled differently from ON and OFF of the switch on apull-down side.

In a case where the resistance elements Ru and Rd are variabletransistors, a configuration may be provided in which the resistanceelements are not switched by two levels of high resistance and lowresistance by the signal VSa (VSb) and are switched by three levels orhigher. In the configuration, a configuration may be provided in which aplurality of resistance elements are switched by the signal VSa (VSb)which is data with two bits or more.

The invention is not limited to the aforementioned embodiments, and forexample, various modifications and applications which will be describedbelow can be made. Aspects of the modifications and application whichwill be described below and are selected arbitrarily or a plurality ofaspects can also foe combined appropriately.

In order to reduce deviation of the voltage Out with respect to thevoltage Vin, the pulse Pls is inserted, and thereby, one of aconfiguration in which one transistor which reduces the deviation amongthe transistors 231 and 232 is turned on in the same manner as in thedrive circuit (Example 1, Example 2), and a configuration in whichresistance of the resistance element Ru for pull-up (the resistanceelement Rd for pull-down) is reduced in the same manner as in the drivecircuit (Example 3, Example 4), may also be selected.

The signal OCa (OCb) can be generated by another circuit without beingoutput from the control unit 110, by analyzing the data dA (dB) asfollows.

For example. In relation to the data dA (dB), discrete values (data)which are temporally adjacent to each other, compared to each other, andif the discrete values are equal, the values are in a voltage-constantperiod, and by determining the discrete values in the constant period,it is possible to determine whether or not a voltage in the constantperiod is higher than or equal to the threshold voltage Vth1. Inaddition, if, when voltage conversion is performed, the discrete valuewhich is temporally later is larger than the discrete value which istemporally prior among the discrete values the value is in a voltageincrease period, and if, when voltage conversion is performed, thediscrete value which is temporally later is smaller than the discretevalue which is temporally prior, the value is in a voltage decreaseperiod.

A signal which is obtained by performing analog conversion may beanalyzed in the same manner as above, while not in the data dA (dB).

In addition, the drive circuit (Example 1, Example 2, Example 3, Example4) may include a diode for blocking a current flowing from the node N2toward a drain terminal of the transistor 231 and a diode for blocking acurrent flowing from a drain terminal of the transistor 232 toward thenode N2.

In the drive circuit (Example 1, Example 2, Example 3, Example 4) thetransistor 231 is configured by a P-channel transistor and thetransistor 232 is configured by an N-channel transistor, but both thetransistors 231 and 232 may be P-channel transistors or N-channeltransistors. However, an output signal of the differential amplifier221, a gate signal at the time of being off by the signal OCa (OCb), andthe like need to be appropriately combined.

In the above description, the liquid ejecting apparatus is described asa printing apparatus, but the liquid ejecting apparatus may be athree-dimensional shaping apparatus which ejects liquid to form athree-dimensional object, a textile printing apparatus which ejectsliquid to print onto a textile, or the like.

In addition, the drive circuit is provided in the main substrate 100,but may be configured to be provided in the carriage 20 (or the headunit 3) together with the drive IC 50. If the drive circuit is providedin the head unit 3, it is not necessary to supply a signal with a largeamplitude through the flexible flat cable 190, and thus, it is possibleto improve anti-noise characteristics.

Furthermore, in the above description, an example is described in whichthe piezoelectric element Pzt for ejecting ink is used as a drive targetof the drive circuit 120 a (120 b), but when considering the drivecircuit 120 a (120 b) which is separated from the printing apparatus,the drive target is not limited to the piezoelectric element Pzt, andcan be applied to all of a load with capacitive components, such as anultrasonic motor, a touch panel, an electrostatic speaker, or a liquidcrystal panel.

What is claimed is:
 1. A liquid ejecting apparatus comprising: anejecting unit that includes a piezoelectric element which is displacedby a drive signal being applied to the piezoelectric element and ejectsliquid in accordance with displacement of the piezoelectric element; afirst differential amplifier that outputs a control signal based on asource drive signal which is a source signal of the drive signal and asignal based on the drive signal; a pair of transistors that include ahigh-side transistor and a low-side transistor which are controlledbased on the control signal and outputs the drive signal from an outputterminal; a second differential amplifier that is different from thefirst differential amplifier and outputs a different voltage between avoltage of the source drive signal and a voltage of the drive signal;and a selector that selects one of the high-side transistor and thelow-side transistor and supplies the control signal to the selectedtransistor, the selector selecting a transistor to which the controlsignal is supplied, based on a logic level of a predetermined selectsignal, the select signal designating selection in the selector, basedon the different voltage output at the second differential amplifier,and the logic level of the select signal being inverted for apredetermined period when the different voltage is larger than or equalto a threshold value.
 2. The liquid ejecting apparatus according toclaim 1, further comprising a first resistance element for pulling upthe output terminal, and a second resistance element for pulling downthe output terminal, wherein a resistance value of the first resistanceelement or a resistance value of the second resistance element varies,and the resistance value changes when a difference between the voltageof the source drive signal and the voltage of the signal based on thedrive signal is larger than or equal to the threshold value.
 3. Theliquid ejecting apparatus according to claim 1, wherein the selectorselects the high-side transistor in a period in which a voltage of thedrive signal increases, and the selector selects the low-side transistorin a period in which the voltage of the drive signal decreases.
 4. Theliquid ejecting apparatus according to claim 1, wherein the selectorselects the high-side transistor in a period in which the drive signalis constant at a voltage higher than or equal to a predeterminedthreshold voltage, and the selector selects the low-side transistor in aperiod in which the drive signal is constant at a voltage lower than thepredetermined threshold voltage.
 5. The liquid ejecting apparatusaccording to claim 4, wherein the threshold voltage is lower than amaximum value of a voltage of the drive signal, and is higher than aminimum value of the voltage of the drive signal.
 6. A drive circuitthat drives a capacitive load using a drive signal, comprising: a firstdifferential amplifier that outputs a control signal based on a sourcedrive signal which is a source signal of the drive signal and a signalbased on the drive signal; a pair of transistors that include ahigh-side transistor and a low-side transistor which are controlledbased on the control signal and outputs the drive signal from an outputterminal; a second differential amplifier that is different from thefirst differential amplifier and outputs a different voltage between avoltage of the source drive signal and a voltage of the drive signal;and a selector that selects one of the high-side transistor and thelow-side transistor and supplies the control signal to the selectedtransistor, the selector selecting a transistor to which the controlsignal is supplied, based on a logic level of a predetermined selectsignal, the select signal designating selection in the selector, basedon the different voltage output at the second differential amplifier,and the logic level of the select signal being inverted for apredetermined period when the different voltage is larger than or equalto a threshold value.
 7. A head unit comprising: a piezoelectric elementwhich is displaced by a drive signal being applied to the piezoelectricelement; and an ejecting unit that includes the piezoelectric elementand ejects liquid in accordance with displacement of the piezoelectricelement, the ejecting unit being driven by a drive circuit whichincludes, a first differential amplifier that outputs a control signalbased on a source drive signal which is a source signal of the drivesignal and a signal based on the drive signal; a pair of transistorsthat include a high-side transistor and a low-side transistor which arecontrolled based on the control signal and outputs the drive signal froman output terminal; a second differential amplifier that is differentfrom the first differential amplifier and outputs a different voltagebetween a voltage of the source drive signal and a voltage of the drivesignal; and a selector that selects one of the high-side transistor andthe low-side transistor and supplies the control signal to the selectedtransistor, the selector selecting a transistor to which the controlsignal is supplied, based on a logic level of a predetermined selectsignal, the select signal designating selection in the selector, basedon the different voltage output at the second differential amplifier,and the logic level of the select signal being inverted for apredetermined period when the different voltage is larger than or equalto a threshold value.
 8. The liquid ejecting apparatus according toclaim 1, further comprising a pulse inserter that insert a pulse intothe select signal to invert the logic level of select signal for thepredetermined period.